Analysis of faults in multi-terminal HVDC grid for definition of test requirements of HVDC circuit breakers
This is the author's version of an article that has been published in this journal. Changes were made to this version by the publisher prior to publication.
The paper provides a detailed analysis of the temporal development of fault currents in a multi-terminal high voltage direct current (MT-HVDC) grid composed of bipolar converter configuration. The sequence of events following the occurrence of a pole-to-ground fault is identified, divided into three distinct periods; namely, sub-module capacitor discharge, arm current decay and ac in-feed periods. The critical parameters that have a significant impact on the fault current in each period are discussed. The impacts of various parameters of the HVDC grid such as the size of the current limiting reactor, ac grid strength as well as the location of the fault within the grid are studied through PSCAD/EMTDC simulation. Then, a fault current interruption process using models of various HVDC circuit breaker technologies and the resulting stresses are studied. Both serve as important inputs to define test procedures. It is found that the HVDC CBs are subjected to not only dc current and voltage stresses but also energy stress. These stresses are translated into test requirements.